Difference Between RISC and CISC Processors

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1. Both are Processor’s architecture that are predominantly used today.
1. Stands for ‘Reduced Instruction Set Computers’ Stands for ‘Complex Instruction Set Computers’.
2. Each instruction utilizes comparatively less number of Instruction cycle before completion of a job. (Main Difference) Each instruction utilizes a much greater number of Instruction cycle before completion of a job.
3. Simpler and Faster Instructions.Single Instruction is normally of one word size. Larger and Complex (slow) Instructions.Single Instruction is normally of more than one word size.
4.  The instructions may be less than 100.
The instructions may be from 120 – 350.
5. RISC processors take about one clock cycle to perform a job. The average clock cycle per instruction (CPI)  of a job in RISC is 1.5.Number of CPI is one as it uses
pipelining. Pipeline in RISC is optimised because of simple instructions and instruction formats.
It takes up multiple clocks for completion of a job. The average clock cycle per instruction (CPI) of a job in CISC is 1 – 20 i.e. Number of Cycles Per Instruction
(CPI) varies from 1-20, depending upon
the instruction used.
6. It has no specific memory unit and hence uses a simple separate hardware to implement instructions.In another words, It does not require external memory for calculations. They are Mostly register-register operations.The only memory access is through explicit LOAD/STORE instructions. It has a specific memory unit to implement complex instructions.In another words, it requires external memory for calculations.Instructions manipulate operands residing in memory.
7. Performance is optimized by focusing (emphasis) on software. Performance is optimized with more focus on hardware.
8. It has only a few instructions in their instruction set i.e. the instruction set is reduced in size and many of these instructions are very primitive in nature. Its instruction set is large hence complex and has a variety of different instructions that can be used for doing any complex operations.
9. They are highly pipelined. They are either not pipelined or less pipelined.
10. Execution time is normally very less. Execution time is normally very high.
11 Code expansion can be a problem. Code expansion is possible.
12. Low cycles per second.
High cycles per second.
13. They are large code sizes. They are small code sizes.
14. Decoding of instructions is simple. Decoding of instructions is complex.
15. Contains large number of general purpose register(GPR) that are primarily used as Global registers, procedure calls, parameterized functions etc. thus, optimized for structured programming. Contains less number of general purpose register inside it. GPRs varies from 8-32. But no support is available for the parameter passing and function calls.
16. Comparatively uses less no. of data types and Simple Addressing Modes in its operation. Uses a variety of data types and a
large number of addressing modes in its operation.
17. Fixed-length instructions usually 32
bits, easy to decode instruction format.
Variable-length instruction formats.
18. It has a hard-wired nature of programming.  It has micro-programmed nature of programming.
19. Widely used in microcontroller application so it is better for particular application. Widely used and suitable for desktop application.
20. Examples are – DEC Alpha, ARC, ARM, MIPS, PA-RISC, PIC, Power Architecture,  SPARC, AMD 29k, Atmel AVR, Blackfin, Intel i860 and i960, Motorola 88000, SuperH etc. Examples are – System/360, VAX, PDP-11, Motorola 68000 family, AMD and Intel x86 etc.

NB :

Both processors architecture are at threat position now due to a new technology called EPIC came into existence.EPIC ( Explicitly Parallel Instruction Computing )is invented by Intel and is in a way, which is a combination of both CISC and RISC. This is theory now that allow the processing of Windows-based as well as UNIX-based applications by the same CPU.        Intel is working on it under code-name Merced. Microsoft is already developing their Win64 standard for it. Like the name says, Merced will be a 64-bit chip. If Intel’s EPIC architecture is successful, it might be the biggest thing.So the future might bring EPIC processors and more CISC processors, while the RISC processors are becoming extinct.

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